Digital Signal Processing

K. Saranya ¹, R. Saran Kumar ¹

Affiliations
1 Department of ECE, Sri Guru Institute of Technology, IN

Abstract

We present two high-speed and low-power full-adder cells designed with an alternative internal logic structure. Two proposed logic of DPL(dual pass transistor logic) and SR-CPL(swing restored CPL)is used. The proposed full adder which has low power and delay is used for two tab FIR filter in DSP applications. The partial product of multiplier in FIR can be replaced using the full adder which reduces delay in the computation of the partial products. Low Power analysis of full adder is done using 0.125um technology S-Edit Tanner EDA tool and simulation is done using Xilinx. The delay of the FIR filter using full adder is found to be less than the conventional FIR filter. This full adder can also be used in ALU operation which contains many arithmetic and logic units. This full adder reduces the delay when used in the operation.

Keywords

Full-Adder, High-Speed, Low-Power.

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K. Saranya ¹

Affiliations
1 Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, IN

Abstract

Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic units designed. Various adder families have been proposed in the past to tradeoff speed, power and area for possible use in ALUs. It includes careful optimization of existing and improved arithmetic units by mixing fast arithmetic units in to slower ones i.e, latency predictor block is used. The improved Ling adder has 40% less power consumption, delay and area than the conventional adders so it is used in the further design of FFT. The throughput, hardware costs, area and power increases due to multiple data path along the stages in FFT approach. By comparing the area, power and delay of the improved adders with conventional, Ling adder is used in Radix-4 FFT approach. The delay of Radix-4 FFT approach with Ling adder gets reduced. The adaptive clocking is applied to the FFT design where the critical path of design is reduced. Power consumption of adders is analyzed using Synopsys design compiler, T-spice S-Edit and delay using Xilinx. The layout of Ling adder is obtained with 180nm technology.

Keywords

Arithmetic Logic Unit, High-Speed Design, Low Power Adders, Latency, Fast Fourier Transform.

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K. Saranya ¹

Affiliations
1 Department of Electronics and Communication Engineering, Sri Guru Institute of Technology, Coimbatore, IN

Abstract

The necessity of designing high speed and low power arithmetic circuits suitable for computationally intensive applications has motivated the design of a high performance arithmetic unit using high speed parallel prefix adder architectures. The present work comprises of designing high performance low power adders. Ling and kogge stone adder is designed for power analysis based on parallel prefix adder structure. For the present work, 0.125μm technology has been used. The average power consumed of the both the adders is found at a supply voltage of 5V. From the analysis made Ling adder is found to consume less power than the kogge stone adder. Ling adders designed based on the ling's algorithm. The whole simulation has been done using TSPICE S-Edit.

Keywords

Arithmetic Unit, Kogge-Stone Adder, Parallel Prefix Structure, Ling Adder.

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